Flat panel displays have become increasingly popular due to their ultra-thin dimensions and low power consumption. Shift registers are used in most flat panel displays. In shift registers implemented with the Gate Drive on Array (GOA) technique, gate drive Integrated Circuits (ICs) can be omitted and thus a manufacturing process can be removed, thereby reducing the manufacturing costs for the flat panel displays while shortening their manufacturing period to some extent.
Hence, the GOA technique has been widely applied to manufacturing of flat panel displays recently. A GOA unit itself has a higher power consumption than a typical gate drive IC. In order to reduce the power consumption of the GOA unit itself, four or more clock (CLK) signals are typically used (the number of clock signals is a multiple of 2) and the frequencies of the clock signals can be reduced, so as to reduce the power consumption. With such design, in each clock period, the high level duration will be longer than the time required for scanning one line by a factor of n (where n is an integer larger than or equal to 2) and two clock signals of adjacent timing sequences will overlap. As shown in FIG. 1, the actual charging period for each gate line is the interval indicated as 2H. With the overlap, each gate line can be turned on in advance and will be fully turned on when a pixel voltage is actually written into that line. In this way, the impact of a rising edge time (Tr) of a gate signal caused by the resistive and capacitive loads of the gate line itself on the charging time can be reduced. Due to the signal delay caused by the parasitic resistance and capacitance of the gate line itself, in order to ensure a correct voltage to be written into each pixel in operation of the display screen, the data signal for each pixel typically needs to be turned off after the gate signal has been turned off. As shown in FIG. 2, the difference between the time at which the gate signal (Vgate) is turned off and the time at which the data signal (Vdata) is turned off mainly depends on a falling edge time (Tf) of the gate signal caused by the resistive and capacitive loads of the gate line itself. That is, the longer Tf is, the shorter the effective charging time (Teff) for each pixel will be. As shown in FIG. 2, Teff<1H.
FIG. 3 shows a specific circuit of a shift register unit implemented with the conventional GOA design. FIG. 4 shows a block diagram of a shift register circuit including a number of cascaded shift register units shown in FIG. 3. Here, the timing sequences of the respective clock signals are shown in FIG. 1. In FIG. 3, the transistors M3 and M4 charge and discharge the output terminal (OUTPUT), respectively. A high level signal is output at the output terminal when the gate of the transistor M3 is at the high level and the clock signal (CLK) is at the high level. Once the scanning of one gate line has completed, the CLK becomes low and the reset signal (RESET) becomes high. At this time, the transistors M2 and M4 are turned on for discharging the gate of the transistor M3 and the output terminal. In this case, the transistors M3 and M4 are in the off and on states, respectively and accordingly only the transistor M4 discharges the output terminal. As shown in FIG. 4, in addition to driving the n-th gate line, the output of the n-th register unit resets the (n−2)-th register unit and serves as the input to the (n+2)-th register unit. In this way, the shift register circuit implemented with the conventional GOA technical can only reduce the impact of Tr on the effective charging time of the pixels by reducing Tr.
For those products having high resolutions or high refreshing rates, the charging time for the pixels is very short. Accordingly, the impact of Tf on the effective charging time of the pixels will be more significant.